1. Field of the Invention
The present invention generally relates to magnetic random access memory (MRAM) devices, and more particularly, the present invention relates to MRAM devices having multi-laminated free magnetic layers, and to methods of fabricating MRAM devices having multi-laminated free magnetic layers.
2. Description of the Related Art
A magnetic random access memory (MRAM) device is a non-volatile memory in which data is stored by programming a magnetic tunnel junction (MTJ). The MTJ is capable of selectively transitioning between two magnetic orientations. The differing resistance values of the two orientations are used to distinguish logic values of the memory cells.
FIG. 1 is a simplified schematic view of an MTJ in each of a low resistance logic “0” magnetic state and a high resistance logic “1” magnetic state. In the figure, reference number 101 denotes a free magnetic layer made of a ferromagnetic material, reference number 102 denotes a tunneling barrier layer, reference number 103 denotes a pinned magnetic layer made of a ferromagnetic material, and reference number 104 denotes a pinning layer made of an anti-ferromagnetic material.
As depicted by the arrows of FIG. 1, the magnetic orientation of the ferromagnetic pinned layer 103 is fixed. This condition may be achieved during manufacture by contacting the anti-ferromagnetic pinning layer 104 with the pinned layer 103 and conducting a heat treatment (at about 200° C. to 300° C.). By application of the magnetic field of the pinning layer 104 during heat treatment, the magnetic spins of the pinned layer 103 become fixed and do not rotate upon later exposure to an external magnetic field. As such, as shown in FIG. 1, the magnetic moment of the pinned layer 103 is fixed in one direction (to the right in FIG. 1). In contrast, with the tunnel barrier layer 102 sandwiched between the pinned magnetic layer 103 and the free magnetic layer 101, the magnetic orientation of the free magnetic layer 101 remains unfixed. As such, the magnetic spins of the free magnetic layer 101 are free to rotate upon later exposure to an external magnetic field. In the MTJ of an MRAM, the free magnetic layer 101 may be stably oriented in one of two directions, i.e., one with its moment parallel to that of the pinned magnetic layer 103, and the other with its moment opposite that of the pinned magnetic layer 103.
As shown in FIG. 1, when the moments of the pinned layer 103 and the free magnetic layer 101 are parallel to one another, the MTJ exhibits a low resistance which may be designated a logic “0” state. In contrast, when the moments extend in opposite directions, the MTJ has a high resistance which may be designated a logic “1” state.
FIG. 2 is a more detailed view of the conventional MTJ. In this cross-sectional view, reference number 1 denotes the pinning layer, reference number 8 denotes the pinned magnetic layer, reference number 9 denotes the tunneling barrier layer, and reference number 14 denotes the free magnetic layer.
As mentioned above, the pinning layer 1 is formed of an anti-ferromagnetic material. Examples include PtMn, IrMn and FeMn.
The pinned magnetic layer 8 is constituted by three layers, i.e., a lower ferromagnetic layer 3, a metal layer 5, and an upper ferromagnetic layer 7. An example of the upper and lower ferromagnetic layers 3 and 7 is CoFe, and an example of the metal layer 5 is Ru.
The tunneling barrier layer 9 is an insulator, and an example thereof is Al2O3.
The free magnetic layer 14 is a two layer structure consisting of a thin lower ferromagnetic layer 11 and a thick upper ferromagnetic layer 13. An example of the thin lower ferromagnetic layer 11 is CoFe, and an example of the thick upper ferromagnetic layer is NiFe.
FIGS. 3(A) and 3(B) illustrate a conventional MRAM memory cell, where FIG. 3(B) is a cross-sectional view taken along line I-I′ of FIG. 3(A).
Referring first to FIG. 3(B), the memory cell includes an MTJ 36, such as that shown in FIG. 2, sandwiched between upper and lower electrodes 37 and 27. The MTJ 36 includes a pinning layer 29 contacting the lower electrode 27, a pinned magnetic layer 31, a tunneling barrier layer 33, and a free magnetic layer 35 contacting the upper electrode 37. The MTJ 36, the upper electrode 37 and the lower electrode 27 together define a programmable magneto-resistive element MR.
The upper electrode 37 contacts a bit line BL extending orthogonally relative to the magnetic orientations of the MTJ 36. In this example, the bit line BL extends into and out of the plane of FIG. 3(B).
A digit line DL is spaced from the bottom of the bottom electrode 27 with an inter-layer dielectric 25 interposed there between. The digit line DL extends parallel to the magnetic orientations of the MTJ 36, and in this example, the digit line DL extends left to right in the diagram of FIG. 3(B).
The digit line DL may be formed over an inter-layer dielectric 23, which in turn may be formed over a substrate 21.
FIG. 3(A) is a top view showing the configuration of the bit line BL and the digit line DL, as well as an outline of the periphery of the magneto-resistive element MR. As shown, the top profile of the magneto-resistive element MR is substantially rectangular, with a length L exceeding a width W. The bit line BL carries a bit line current IBL, and extends length-wise along the width W of the magneto-resistive element MR. Further, the bit line BL is wide enough to substantially overlap the length L of the magneto-resistive element MR. The digit line DL extends orthogonally to the bit line BL, along the length L of the magneto-resistive element MR. Further, the digit line DL is wide enough to substantially overlap the width W of the magneto-resistive element MR.
As shown in FIG. 3(A), a hard magnetic axis Hhard extends in the direction of the shorter width W, and an easy magnetic axis Heasy extends in the direction of the longer length L.
FIG. 4 illustrates a conventional MRAM array which includes a plurality of intersecting bit lines BL1, BL2, . . . , BLn, and digit lines DL1, DL2, . . . , DLn. Write current ID is applied to each digit line, and write current IB is applied to each bit line. Magneto-resistive elements MR12, MR22, . . . , MRn2 are located along the bit lines at the intersections with the digit lines.
FIG. 5(A) is a cross-sectional schematic view of an MRAM cell including a transistor for reading a logic state of the cell, and FIG. 5(B) is a circuit representation of the same. A magneto-resistive element MRl is configured like that shown in FIG. 3(B) and includes an upper electrode 77, a lower electrode 55, and an MTJ 75 sandwiched between the upper electrode 77 and the lower electrode 55. The MTJ 75 includes a pinning layer 57, a pinned magnetic layer 64, an insulating barrier layer 65, and a free magnetic layer 73.
Reference numbers 53a, 53b, 53c and 111 denote interlayer dielectric layers (ILDs). A bit line BL is connected to the upper electrode 73 of the magneto-resistive element MR1 and is located on a top surface of the ILD 111. A digit line DL extends orthogonally to the bit line BL on an upper surface of the ILD 53b and below the magneto-resistive element MR1.
A transistor TA is defined by a word line (gate) WL, a source S and a drain D. The source S and drain D are formed in a substrate 51. The source S is connected to a source pad 103S via a contact plug 101s. The drain D is connected to the lower electrode 55 via upper and lower drain pads 107, 103d, and contact plugs 109, 105 and 101d. 
A read operation is executed when a signal on the word line WL is sufficient to render the transistor TA in a conductive state. Current then flows from the bit line BL through the magneto-resistive element MR1. When the magneto-resistive element MR1 is programmed in a low resistance state (logic “0”), a relatively large amount of current will flow through the transistor TA. When the magneto-resistive element MR1 is programmed in a high resistance state (logic “1”), a relatively small amount of current will flow through the transistor TA. Thus, the amount of current flow can be used to determine the programmed state of the magneto-resistive element.
The sensing margin of the magneto-resistive element is defined by the difference or ratio between the high resistive state Rmax and low resistance state Rmin of the magneto-resistive element MR1. Unfortunately, however, magnetic imperfections in the free magnetic layer of the MTJ adversely impact the sensing margin.
FIG. 6(A) depicts a free magnetic layer 14 having an external magnetic field H applied thereto. Each of the encircled areas denotes a domain of the free magnetic layer 14. Upon application of the external magnetic field H, the magnetized direction of each domain should be parallel to the magnetic field H. However, as can be seen in FIG. 6(A), some of the magnetized directions are not parallel to the field H, particularly at the domain boundary. This reduces the sensing margin. Accordingly, to overcome the non-parallel moments at the domain boundaries, it becomes necessary to strengthen the magnetic field H by increasing the currents applied to the bit line and digit line. The result is increased power consumption.
As shown at the right side of FIG. 6(B), the free magnetic layer is ideally formed of uniformly arranged grains. However, has shown by the enlarged view at the left side of FIG. 6(B), thick ferromagnetic layers exhibit large and irregular grains. The result is many domain boundaries that degrade magnetization uniformity.
FIG. 7 is a hysteresis loop for explaining the effects of magnetic imperfections in the MTJ. The solid lined portion is the hysteresis loop for an ideal MTJ, and the dashed line to the right shows a loop characteristic of a conventional MRAM.
As shown, in the case of an ideal MTJ, when the magnetic flux Heasy is +H1 (Oe), the magnetic moment of the free magnetic layer completely rotates in one direction and the MTJ resistance Rw (Ω) goes from Rmin to Rmax. On the other hand, when the magnetic flux Heasy becomes −H1 (Oe), the magnetic moment rotates in the other direction and the MTJ resistance Rw goes from Rmax to Rmin. Also, so long as the magnetic flux Heasy is greater than −H1 and less than +H1, there is no change in the MTJ resistance Rw.
The conventional MRAM, however, does not operate ideally, and instead the MTJ resistance Rw only begins to increase at “k” when the magnetic flux becomes +H1. The rotation of the magnetic moment of the free magnetic layer is gradual, and accordingly, the MTJ resistance Rw gradually increases with an increase in the magnetic flux Heasy. In order to achieve Rmax, an increased magnetic flux of +H1′ is needed, which means additional power must be consumed.
Incidentally, as mentioned previously, the conventional free magnetic layer consists of a lower layer of CoFe, and an upper layer of NiFe. The CoFe layer is provided to increase the sensing margin, i.e., the difference between Rmax and Rmin in FIG. 7. On the other hand, the NiFe layer is intended to decrease the width Q of the hysteresis loop of FIG. 7, which would mean less power consumption.
FIG. 8(A) shows the switching characteristic of an ideal MTJ in relation to the application of the magnetic flux Heasy and the magnetic flux Hhard. A write is achieved when the magnetic flux Heasy is HME (Oe), or when the magnetic flux Hhard is HMH (Oe). In addition, the curved lines BDL in each quadrant denote the minimum combination of Heasy and Hhard to write the MTJ, i.e., to switch the direction of the moment of the free magnetic layer of the MTJ. Thus, a write region WR is located outside the curved lines BDL, and a read region RR is located within the curved lines BDL. The ideal MTJ can be reliable written at point P1, where a magnetic flux Heasy is 20 Oe and the magnetic flux Hhard is 20 Oe.
For comparison with the ideal MTJ, FIG. 8(B) shows the switching characteristics of the conventional MTJ. As shown, the ideal write flux P2 (Heasy=Hhard=20 Oe) will not in most instances switch the magnetic moment of the free magnetic layer of the conventional MTJ. Rather, a magnetic flux where both Hheasy and Hhard are about 40 Oe is needed to reliably write the MTJ.
Further, as shown in FIG. 8(B), the conventional MTJ is characterized by a wide write variation 1W. This can be modeled as two ideal MTJs as shown in FIG. 9, wherein an inner MTJ1 corresponds to the inner boundary of the write variation 1W, and the outer MTJ2 corresponds to the outer boundary of the write variation 1W. In order to reliably write the outer MTJ2, a write flux such as that shown at point P3 is needed. However, such a write flux is well in excess of both HME′ and HMH′ of the inner transistor MTJ1. This can cause write errors with respect to the inner transistor MTJ1.
In summary, magnetic imperfections in the conventional magnetic tunnel junction can result in both increased power consumption and operational faults.